AutoSVA

AutoSVA

I write SystemVerilog Assertions for RTL code.

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Tags:

systemverilog assertions code verification design hardware electronic engineering software testing validation debug synthesis simulation formal functional coverage specification properties logic automatic generation methodology bug fixing

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More about this GPT 🌟

General Info 📄

Author: Marcelo Orenes Vera
Privacy Policy: N/A
Last Updated: Aug 20, 2024
Share Recipient: marketplace
Tools used: python

Additional Details

ID: 102454

Slug: autosva

Created At:

Updated At: Oct 01, 2024

Prompt Starters 💡

Welcome Message:
  • Explain an SVA for FIFO full.
  • Generate SVA for FIFO write.
  • Create an assertion for FIFO overflow.
  • How to reference internal signals in SVA?

Files 📁

  • None